1. Field of the Invention
This invention relates generally to data processing systems and more particularly to the exchange of logic signals on a system bus in the data processing system. The exchange of logic signals by means of a system bus can compromise the integrity of the signal exchange unless provision is made to permit the transient signal conditions, resulting from the activation and deactivation of the driver circuits applying the signals to system bus, to come to equilibrium.
2. Description of the Related Art
Referring to FIG. 1, a typical data processing system is shown. The data processing system includes at least one central processing unit 10 (or 11), at least one input/output device 13 (or 14), at least one memory unit 15 and a system bus 19 coupling the plurality of units or subsystems of the data processing system. The central processing unit processes groups of logic signals according to software and/or firmware instructions. The logic signal groups to be processed are typically stored in the memory unit 15. A console unit 12 can be coupled to the central processing unit(s) and typically includes the apparatus and stored instructions to initialize the system and can act as a terminal during the operation of the data processing system. The input/output units provide the interface to the remainder of the data processing system to terminal units, mass storage units, communication units, and any other units to be coupled to the data processing system. The detailed function of the units coupled to the system bus is less important than the fact that these units operate autonomously and communicate with the remainder of the data processing units primarily by means of the system bus.
Referring next to FIG. 2, the technique for applying logic signals to the system bus is illustrated. The system bus 19 is compromised of a multiplicity of conducting elements, 19a through 19g. The conducting elements, as the cycle times of the data processing systems have decreased, have acquired the characteristics of transmission lines and must, for example, be terminated in such manner (not shown) as to avoid reflections. Each data processing unit that can apply signals to the system has a multiplicity of transistors coupled to the system bus. For example, data processing system unit 21 has the emitter elements of transistors 21a through 21g coupled to system bus conductors 19a through 19g respectively, while data processing system unit 23 has the emitter elements of transistors 23a through 23g also coupled to conducting elements 19a through 19g. When data processing system unit 21 is to place a group of logic signals on the system bus, the base terminals of the transistors that are to assume a first logic state are maintained at a high level (in which the associated transistors are conducting), while the base elements of the transistors that are to assume a second logic state are maintained at low level (in which the associated transistors are in a nonconducting state).
It will be clear that the transient conditions on the system bus that result from a change in state of conductivity of a coupled transistor pair can remain for the length of time needed for the propagation, whichever is longer, of the signal (1) from the data processing system unit establishing the logic state of the bus to the data processing system units identifying the state of the system bus, or (2) from the unit releasing the logic state of the bus to the unit(s) identifying the state of the bus.
However, the transient conditions on the system bus can remain for a longer period of time as can be understood by reference to FIG. 3 and FIG. 4. When the initial state of the conductor 19x of the system bus is the first (high) logic state in which the transistor 21x, associated with corresponding data processing subsystem 21, is in the conducting state, the voltage level along conductor 19x is essentially constant, position 21 indicating the location on the system bus conductor of data processing system unit 21 and position 23 indicating the location on the system bus conductor of data processing system unit 23. This condition is shown by the curve in FIG. 4a. When the next consecutive state in the system is one in which transistor 21x is in a nonconducting state and transistor 23x is in a conducting state, then, immediately after the new state is entered, transistor 21x is rendered nonconducting. As shown in the curve in FIG. 4b, immediately after the new state is entered, the low voltage level indicating the application of no logic level propagates along the conducting element 19x. Turning now to the operation of the transistor 23x, the base of transistor 23x has a voltage applied thereto to place this transistor in a conducting state. However, because the signal resulting from ceasing of the prior conduction of transistor 21x has not yet propagated to the position of transistor 23x on the system bus conductor, transistor 23x may not be in the conducting state even though the voltage level of the base is at a level where conduction of the transistor normally takes place. At a later time, as shown in FIG. 4c, the effect of rendering transistor 21x nonconducting will have propagated to position 23. Immediately thereafter, as shown in FIG. 4d, transistor 23 becomes conducting and a voltage level signal is propagated along the system bus conductor. After a period of time, the voltage level resulting from initiation of conduction of transistor 23x will reach position 21, as shown in FIG. 4e. Therefore, it will be clear that transient signal effects on the system bus can persist for a longer period than the time calculated for the transients to propagate along the distance defined by the physical separation of the data processing system elements.
It has been known in the related art to provide a timing cycle for the data processing system that can accommodate the longest required time. However, the adjustment of the system timing cycle to the worst case can be inefficient because for selected types of access to the system bus, a plurality of bus access cycles can occur from a single data processing subsystem without interruption. The excessively long system cycle time would make such a transfer of signals unnecessarily long in addition to the overall compromise of the system performance resulting from a long system cycle time.
A need has therefore been felt for apparatus and method of operation for the system bus that would permit the cycle time of the data processing system to remain short while simultaneously permitting any transient conditions on the system bus to decay, thereby maintaining the integrity of logic state imposed on the data processing system bus.